Memory devices, such as random access memory (RAM), flash memory, and hard disk drives, can contain storage errors. These errors can result from physical factors of the memory device or other factors. Memory errors can lead to erroneous data being read from the memory device, and frequent or repeated errors can result in poor device operation.
In order to reduce the impact of memory storage errors, a device can employ error correction techniques. For example, a memory device can store error correction code (ECC) data for memory locations in the memory device. The ECC data contains parity or other data that allows the device to detect errors. In addition, the ECC data can contain error correction data that allows the device to correct detected errors.
To improve memory reliability, error correction can be performed each time data is read from a memory. However, performing error correction can reduce system efficiency. For example, an error correction operation on 64 bits of data with eight error correction bits may require 20 or more levels of combinatorial logic. Thus, performing error correction can increase the data latency, or if operating in a pipelined system, the number of wait states experienced by a processor when reading from the memory.
Therefore, it is desirable to provide a device that performs error correction without undesirably reducing system efficiency.
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